/***************************************************************************************
* Copyright (c) 2014-2022 Zihao Yu, Nanjing University
*
* NEMU is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
*          http://license.coscl.org.cn/MulanPSL2
*
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
*
* See the Mulan PSL v2 for more details.
***************************************************************************************/

#include "local-include/reg.h"
#include <cpu/cpu.h>
#include <cpu/ifetch.h>
#include <cpu/decode.h>
#include <tracers.h>
#include <stdint.h>

#define Reg(i) gpr(i)
#define Csr(i) csr(i)
#define Mr vaddr_read
#define Mw vaddr_write
extern uint8_t current_status;

enum {
  TYPE_I, TYPE_U, TYPE_S, TYPE_J,
  TYPE_R, TYPE_B, TYPE_N
};

#define src1R() do { *src1 = Reg(rs1); } while (0)
#define src2R() do { *src2 = Reg(rs2); } while (0)
#define immI() do { *imm = SEXT(BITS(i, 31, 20), 12); } while(0)
#define immU() do { *imm = SEXT(BITS(i, 31, 12), 20) << 12; } while(0)
#define immJ() do { *imm = (SEXT(BITS(i, 31, 31), 1) << 20) | (BITS(i, 19, 12) << 12) | (BITS(i, 20, 20) << 11) | (BITS(i, 30, 21) << 1) ; } while(0)
#define immS() do { *imm = (SEXT(BITS(i, 31, 25), 7) << 5) | BITS(i, 11, 7); } while(0)
#define immB() do { *imm = (SEXT(BITS(i, 31, 31), 1) << 12 | BITS(i, 7, 7) << 11 | BITS(i, 30, 25) << 5 | BITS(i, 11,  8) << 1); } while(0)
static void decode_operand(Decode *s, int *dest, word_t *src1, word_t *src2, word_t *imm, int type) {
  uint32_t i = s->isa.inst.val;
  int rd  = BITS(i, 11, 7);
  int rs1 = BITS(i, 19, 15);
  int rs2 = BITS(i, 24, 20);
  *dest = rd;
  switch (type) {
    case TYPE_I: src1R();          immI(); break;
    case TYPE_U:                   immU(); break;
    case TYPE_J:                   immJ(); break;
    case TYPE_S: src1R(); src2R(); immS(); break;
    case TYPE_B: src1R(); src2R(); immB(); break;
    case TYPE_R: src1R(); src2R();         break;
  }
}

static int decode_exec(Decode *s) {
  int dest = 0;
  int uimm = BITS(s->isa.inst.val, 19, 15);
  word_t src1 = 0, src2 = 0, imm = 0;
  s->dnpc = s->snpc;

#define INSTPAT_INST(s) ((s)->isa.inst.val)
#define INSTPAT_MATCH(s, name, type, ... /* execute body */ ) { \
  decode_operand(s, &dest, &src1, &src2, &imm, concat(TYPE_, type)); \
  __VA_ARGS__ ; \
}

  INSTPAT_START();
  INSTPAT("??????? ????? ????? ??? ????? 01101 11", lui    , U, Reg(dest) = imm);
  INSTPAT("??????? ????? ????? ??? ????? 00101 11", auipc  , U, Reg(dest) = s->pc + imm);
  
  INSTPAT("??????? ????? ????? 000 ????? 00000 11", lb     , I, Reg(dest) = SEXT(Mr(src1 + imm, 1), 8));
  INSTPAT("??????? ????? ????? 001 ????? 00000 11", lh     , I, Reg(dest) = SEXT(Mr(src1 + imm, 2), 16));
  INSTPAT("??????? ????? ????? 010 ????? 00000 11", lw     , I, Reg(dest) = SEXT(Mr(src1 + imm, 4), 32));
  INSTPAT("??????? ????? ????? 011 ????? 00000 11", ld     , I, Reg(dest) = Mr(src1 + imm, 8));
  INSTPAT("??????? ????? ????? 100 ????? 00000 11", lbu    , I, Reg(dest) = Mr(src1 + imm, 1));
  INSTPAT("??????? ????? ????? 101 ????? 00000 11", lhu    , I, Reg(dest) = Mr(src1 + imm, 2));
  INSTPAT("??????? ????? ????? 110 ????? 00000 11", lwu    , I, Reg(dest) = Mr(src1 + imm, 4));
  INSTPAT("??????? ????? ????? 000 ????? 00100 11", addi   , I, Reg(dest) = src1 + imm);
  INSTPAT("??????? ????? ????? 010 ????? 00100 11", slti   , I, Reg(dest) = (sword_t)src1 < (sword_t)imm ? 1 : 0);
  INSTPAT("??????? ????? ????? 011 ????? 00100 11", sltiu  , I, Reg(dest) = src1 < imm ? 1 : 0);
  INSTPAT("??????? ????? ????? 100 ????? 00100 11", xori   , I, Reg(dest) = src1 ^ imm);
  INSTPAT("??????? ????? ????? 110 ????? 00100 11", ori    , I, Reg(dest) = src1 | imm);
  INSTPAT("??????? ????? ????? 111 ????? 00100 11", andi   , I, Reg(dest) = src1 & imm);
  INSTPAT("000000? ????? ????? 001 ????? 00100 11", slli   , I, Reg(dest) = src1 << imm);
  INSTPAT("000000? ????? ????? 101 ????? 00100 11", srli   , I, Reg(dest) = src1 >> imm);
  INSTPAT("010000? ????? ????? 101 ????? 00100 11", srai   , I, Reg(dest) = (sword_t)src1 >> imm);
  INSTPAT("??????? ????? ????? 000 ????? 11001 11", jalr   , I, Reg(dest) = s->snpc; s->dnpc = src1 + imm);
  INSTPAT("??????? ????? ????? 000 ????? 00110 11", addiw  , I, Reg(dest) = SEXT(src1 + imm, 32));
  INSTPAT("0000000 ????? ????? 001 ????? 00110 11", slliw  , I, Reg(dest) = SEXT(BITS(src1, 31, 0) << imm, 32));
  INSTPAT("0000000 ????? ????? 101 ????? 00110 11", srliw  , I, Reg(dest) = SEXT(BITS(src1, 31, 0) >> imm, 32));
  INSTPAT("0100000 ????? ????? 101 ????? 00110 11", sraiw  , I, Reg(dest) = SEXT((sword_t)SEXT(BITS(src1, 31, 0), 32) >> imm, 32));
  INSTPAT("??????? ????? ????? 001 ????? 11100 11", csrrw  , I, Reg(dest) = Csr(imm); Csr(imm) = src1);
  INSTPAT("??????? ????? ????? 010 ????? 11100 11", csrrs  , I, Reg(dest) = Csr(imm); Csr(imm) |= src1);
  INSTPAT("??????? ????? ????? 011 ????? 11100 11", csrrc  , I, Reg(dest) = Csr(imm); Csr(imm) &= ~src1);
  INSTPAT("??????? ????? ????? 101 ????? 11100 11", csrrwi , I, Reg(dest) = Csr(imm); Csr(imm) = uimm);
  INSTPAT("??????? ????? ????? 110 ????? 11100 11", csrrsi , I, Reg(dest) = Csr(imm); Csr(imm) |= uimm);
  INSTPAT("??????? ????? ????? 111 ????? 11100 11", csrrci , I, Reg(dest) = Csr(imm); Csr(imm) &= uimm);
  INSTPAT("0011000 00010 00000 000 00000 11100 11", mret   , I, 
    word_t mstatus = csrs("mstatus"); 
    csrs("mstatus") = ((mstatus & 0xFFFFF0000) | 0x0080 | (BITS(mstatus, 7, 7) << 3)); 
    s->dnpc = csrs("mepc"); 
    current_status = ((mstatus >> 11) & 3); 
    etrace(false, cpu.pc, mstatus);
  );

  INSTPAT("0000000 ????? ????? 000 ????? 01100 11", add    , R, Reg(dest) = src1 + src2);
  INSTPAT("0100000 ????? ????? 000 ????? 01100 11", sub    , R, Reg(dest) = src1 - src2);
  INSTPAT("0000000 ????? ????? 010 ????? 01100 11", slt    , R, Reg(dest) = (sword_t)src1 <(sword_t)src2);
  INSTPAT("0000000 ????? ????? 011 ????? 01100 11", sltu   , R, Reg(dest) = src1 < src2);
  INSTPAT("0000000 ????? ????? 110 ????? 01100 11", or     , R, Reg(dest) = src1 | src2);
  INSTPAT("0000000 ????? ????? 111 ????? 01100 11", and    , R, Reg(dest) = src1 & src2);
  INSTPAT("0000000 ????? ????? 100 ????? 01100 11", xor    , R, Reg(dest) = src1 ^ src2);
  INSTPAT("0000000 ????? ????? 000 ????? 01110 11", addw   , R, Reg(dest) = SEXT(BITS(src1, 31, 0) + BITS(src2, 31, 0), 32));
  INSTPAT("0100000 ????? ????? 000 ????? 01110 11", subw   , R, Reg(dest) = SEXT(BITS(src1, 31, 0) - BITS(src2, 31, 0), 32));
  INSTPAT("0000001 ????? ????? 000 ????? 01100 11", mul    , R, Reg(dest) = src1 * src2);
  INSTPAT("0000001 ????? ????? 000 ????? 01110 11", mulw   , R, Reg(dest) = SEXT(BITS(src1, 31, 0) * BITS(src2, 31, 0), 32));
  INSTPAT("0000001 ????? ????? 001 ????? 01100 11", mulh   , R, Reg(dest) = ((__int128_t)(int64_t)src1 * (__int128_t)(int64_t)src2) >> 64);
  INSTPAT("0000001 ????? ????? 010 ????? 01100 11", mulhsu , R, Reg(dest) = ((__int128_t)(int64_t)src1 * (__uint128_t)src2) >> 64);
  INSTPAT("0000001 ????? ????? 011 ????? 01100 11", mulhu  , R, Reg(dest) = ((__uint128_t)src1 * (__uint128_t)src2) >> 64);
  INSTPAT("0000001 ????? ????? 100 ????? 01100 11", div    , R, Reg(dest) = (sword_t)src1 / (sword_t)src2);
  INSTPAT("0000001 ????? ????? 101 ????? 01100 11", divu   , R, Reg(dest) = src1 / src2);
  INSTPAT("0000001 ????? ????? 110 ????? 01100 11", rem    , R, Reg(dest) = (sword_t)src1 % (sword_t)src2);
  INSTPAT("0000001 ????? ????? 111 ????? 01100 11", remu   , R, Reg(dest) = src1 % src2);
  INSTPAT("0000001 ????? ????? 110 ????? 01110 11", remw   , R, Reg(dest) = (sword_t)SEXT(BITS(src1, 31, 0), 32) % (sword_t)SEXT(BITS(src2, 31, 0), 32));
  INSTPAT("0000001 ????? ????? 111 ????? 01110 11", remuw  , R, Reg(dest) = SEXT(BITS(src1, 31, 0) % BITS(src2, 31, 0), 32));
  INSTPAT("0000001 ????? ????? 100 ????? 01110 11", divw   , R, Reg(dest) = (sword_t)SEXT(BITS(src1, 31, 0), 32) / (sword_t)SEXT(BITS(src2, 31, 0), 32));
  INSTPAT("0000001 ????? ????? 101 ????? 01110 11", divuw  , R, Reg(dest) = SEXT(BITS(src1, 31, 0) / BITS(src2, 31, 0), 32));
  INSTPAT("0000000 ????? ????? 001 ????? 01110 11", sllw   , R, Reg(dest) = SEXT(BITS(src1, 31, 0) << BITS(src2, 4, 0), 32));
  INSTPAT("0000000 ????? ????? 101 ????? 01110 11", srlw   , R, Reg(dest) = SEXT(BITS(src1, 31, 0) >> BITS(src2, 4, 0), 32));
  INSTPAT("0100000 ????? ????? 101 ????? 01110 11", sraw   , R, Reg(dest) = SEXT((sword_t)SEXT(BITS(src1, 31, 0), 32) >> BITS(src2, 4, 0), 32));
  INSTPAT("0000000 ????? ????? 001 ????? 01100 11", sll    , R, Reg(dest) = src1 << src2);
  INSTPAT("0000000 ????? ????? 101 ????? 01100 11", srl    , R, Reg(dest) = src1 >> BITS(src2, 4, 0));
  INSTPAT("0100000 ????? ????? 001 ????? 01100 11", sra    , R, Reg(dest) = (sword_t)src1 >> BITS(src2, 4, 0));

  INSTPAT("??????? ????? ????? 000 ????? 01000 11", sb     , S, Mw(src1 + imm, 1, src2));
  INSTPAT("??????? ????? ????? 001 ????? 01000 11", sh     , S, Mw(src1 + imm, 2, src2));
  INSTPAT("??????? ????? ????? 010 ????? 01000 11", sw     , S, Mw(src1 + imm, 4, src2));
  INSTPAT("??????? ????? ????? 011 ????? 01000 11", sd     , S, Mw(src1 + imm, 8, src2));
  
  INSTPAT("??????? ????? ????? ??? ????? 11011 11", jal    , J, Reg(dest) = s->snpc; s->dnpc = s->pc + imm);
  
  INSTPAT("??????? ????? ????? 000 ????? 11000 11", beq    , B, s->dnpc = src1 == src2 ? s->pc + imm : s->snpc);
  INSTPAT("??????? ????? ????? 001 ????? 11000 11", bne    , B, s->dnpc = src1 != src2 ? s->pc + imm : s->snpc);
  INSTPAT("??????? ????? ????? 100 ????? 11000 11", blt    , B, s->dnpc = (sword_t)src1 < (sword_t)src2 ? s->pc + imm : s->snpc);
  INSTPAT("??????? ????? ????? 101 ????? 11000 11", bge    , B, s->dnpc = (sword_t)src1 >= (sword_t)src2 ? s->pc + imm : s->snpc);
  INSTPAT("??????? ????? ????? 110 ????? 11000 11", bltu   , B, s->dnpc = src1 < src2 ? s->pc + imm : s->snpc);
  INSTPAT("??????? ????? ????? 111 ????? 11000 11", bgeu   , B, s->dnpc = src1 >= src2 ? s->pc + imm : s->snpc);
  
  INSTPAT("0000000 00000 00000 000 00000 11100 11", ecall  , N, s->dnpc = isa_raise_intr(current_status == PRIV_U ? 0x8 : 0xb, csrs("mtvec")));
  INSTPAT("0000000 00001 00000 000 00000 11100 11", ebreak , N, NEMUTRAP(s->pc, Reg(10))); // R(10) is $a0
  INSTPAT("??????? ????? ????? ??? ????? ????? ??", inv    , N, INV(s->pc));
  INSTPAT_END();

  Reg(0) = 0; // reset $zero to 0
#ifdef CONFIG_ITRACE
  Log("pc= %lx, dnpc= %lx, snpc= %lx", s->pc, s->dnpc, s->snpc);
#endif
  return 0;
}

int isa_exec_once(Decode *s) {
  s->isa.inst.val = inst_fetch(&s->snpc, 4);
  return decode_exec(s);
}
